Analog to digital signal conversion



Aug. 18, 1964 G. CURRIE 3,145,376

ANALOG TO DIGITAL SIGNAL CONVERSION Filed March 14, 1960 2 SheetsSheet lANALOG IN PUT RING COUNTER BY ROM-n ATTORNEY Aug 18, 1964 GJCURRIE3,145,376

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expressed in digital numbers.

United States Patent 3,145,376 ANALOG T0 DIGITAL SEGNAL CQNVERfiiGNGerard Currie, Santa Clara, Calif., assignor to General Precision, Inc,Bingharnton, N.Y., a corporation of Delaware Filed Mar. 14, 196d, Ser.No. 14,874 11 Claims. (Cl. 34034'7) This invention relates to analog anddigital electronic computing circuits, and more particularly to suchcircuits for converting analog signals representative of numericalquantities into digital signals coded to represent the same numericalquantities.

As is generally well-known, there are two basic types of computingcircuits-analog and digital. In an analog circuit there is a directcorrespondence or an analogy between the quantities undergoingcalculations and certain electrical quantities, mostly voltages,existing at various points in the circuit. In a digital circuit, itemsof data are represented by coded combinations of signals in which eachsignal may exist in one of a finite number (usually only two) ofdiscrete quantities. The circuits of analog and digital computers arequite different from each other, but the need often arises forconverting an analog signal in a corresponding digital signal, or viceversa. There have been various circuits devised for analog-to-digital ordigital-to-analog signal conversion.

In an electronic computing system a plurality of analog signals may bederived each representing a quantity to be Although the computing systemcould be provided with several analog to digital converting circuits, aneconomy may be effected by providing a single multiplexed analog todigital converting circuit which operates upon the various analogsignals on a time sharing basis. The various analog inputs may beapplied to an input switching or commutator arrangement such that thevarious analog signals are impressed in sequence upon a single convertercircuit, and corresponding digital output signals are developed in thesame time sequence.

Analog to digital conversion may be accomplished by applying the analogsignals to the input or summing point of an operational amplifier, andthen selectively combining therewith digitally derived voltages toestablish a predetermined signal level in the amplifier. For example,the input level of the amplifier may be preset to Zero or groundpotential, and a positive analog voltage must be balanced with anappropriate negative digitally derived voltage to re-establish the inputvoltage at zero. The circuit for generating the digital balancingvoltages may simultaneously develop the digital output signal.

Operational amplifiers are amplifiers which are capable of performingone or more mathematical operations such as summing, integrating ordifferentiating and are usually of the type capable of amplifying directcurrents. This type amplifier may be subject to an error resulting fromdirect current drift. Amplifier drift may be temporarily corrected by amanual adjustment, but this adjustment will not continue to be correct,as the amplifier remains in operation and therefore an initialadjustment may later become faulty.

In the multiplexed or time sharing analog-to-digital conversion systems,a further error may be introduced because of leakage currents passed bythe switching or commutator input circuit. Such leakage currents areindividually of slight consequence, however, as more and more analogchannels are added to the input circuit, the leakage currents becomecumulative in their effect and cannot be ignored. Heretofore, amultiplexed analog-todigital conversion system has been limited toapproximate- -ly 30 or 40 separate analog inputs because the combined3,145,376 Patented Aug. 18, 1964 ice leakage currents from more inputcircuits would cause a combined error which could not be tolerated.

It is an object of this invention to provide an improved method andmeans for converting analog signals into digital signals wherein anerror correction arrangement is provided to compensate for both thedirect current drift of the amplifier and the switching or commutatorleakage of the multiple analog input circuits.

It is a further object of this invention to provide an improvedmultiplexed analog-to-digital converter with an input switchingarrangement and error correction arrange ment such that the number ofanalog input channels may be increased substantially beyond presentlimitations and more particularly it is an object to provide an improvedinput switching arrangement for multiplexing many analog inputs on atime sharing basis to a single analog-to-digital signal conversioncircuit.

Other objects and many of the attendant advantages of this invention maybe readily appreciated as they become better understood by reference tothe following detailed description when considered in connection withthe accompanying drawings in which:

FIGURE 1 is a circuit diagram partially in blocks of the analog todigital signal conversion apparatus of this invention;

FIGURE 2 is a timing diagram of the timing or clock pulses used by thisinvention; and

FIGURE 3 is a circuit diagram more fully illustrating the logic anddigital ladder circuits which were shown as simple blocks in FIGURE 1.

Briefly stated, according to a preferred embodiment of this invention, aplurality of analog input signals may be applied to respective inputterminals 11, 12, 13 and 14 which are coupled to an operationalamplifier 15 through resistive networks including resistors 16 through23 arranged in pairs as shown in FIGURE 1. A further pair of resistors24 and 25 is coupled between a reference potential input terminal 26 andthe input summing point 27 of the amplifier 15. The reference potential26 may be that of ground as indicated in FIGURE 1 or alternative- 1y, itmay be any desired constant voltage. A plurality of transistors 28through 32 constitute an input commutator or switching means. Whenconductive, the transistors shunt the analog signals to ground; and whena selected transistor is non-conductive the corresponding analog signalis coupled to the input of the amplifier 15.

The amplifier 15 may be of conventional design-preferably having a lowinput impedance and being coupled to pass direct currents. Certainoperational amplifiers described in Electronic Analog Computers by Kornand Korn, 1956 Edition, pages 214 to 223 would be suitable for use asthe amplifier 15 in this invention.

A cycle of operation is initiated when the transistor 28 is renderednon-conductive by a control means such as a ring counter 34, whereuponthe reference voltage (ground potential) of the terminal 26 is coupledto the summing point 27 of the amplifier 15 through the resistors 24 and25. During this interavl the output at a point 35 should likewise remainat zero potential, but due to the inaccuracies and spurious currentsfrom transistors 28 through 32, and due to the drift of the amplifier 15the potential at the output point 35 may be of a substantial value.During this initial period, a first digital ladder circuit 36 willdigitally generate a correction voltage which is passed to the summingpoint 27 of the amplifier through a resistive coupling 37 and theamplifier signal level is restored to zero (or other reference voltage).As the ring counter 34 is stepped through the remainder of the operatingcycle, the transistors 29, 30, 31 and 32 become non-conductive insequence, whereby the analog inputs of the terminals 11, 12, 13 and 14are sequentially impressed upon the summing point 27 of the amplifier15. During the reens-5,2376

or mainder of the cycle, the correction voltage from the ladder 36remains impressed upon the input of the amplifier 15', and a seconddigital ladder circuit 39 becomes operative to develop and impressdigital voltages upon the amplifier summing-point 27 through a couplingresistor 40. Digital outputsignals are generated to correspond to thevoltages impressed upon the amplifying summing point 27 and will appearat terminals 41 through 4 Thus the transistor 2% controlled by the ringcounter 34 serves to impress a'reference potential upon the summingpoint 27 and amplifying circuit 15, and a digital correction voltage isobtained from the ladder circuits representative of error introduced inthe amplifying circuit. The transistors 23-32 serve to impress theanalog signals on the amplifying circuit 15 and output signals areobtained therefrom which will appear on the lead 35. The ladder circuits36 continue to supply the error correcting voltage to the summing point27, and thereby the analog signals are corrected in accordance with thedigital correction voltage.

The timing cycle may be best understood by reference to FIGURE 2. Amultivibrator 4-6 (FKGURE 1) may "be used to generate a square wave asshown by the first curve indicated as MV. This multivibrator may be ofconventional design, for example, the circuit shown and described onpage 80 and on page 4-43 or Digital Computer Components and Circuits byR. K. Richards, published by D. Van Nostrand Company. This multivibratoras may be couple to a ring counter circuit 4'7, which may also be ofconventional design such as shown in the Richards book supra on page 89,447, or 459. The ring counter will produce sub-cycles of sequentially.timcd pulses at output terminals indicated in FIGURE 1 as TP TF TF TFTR; and TF As shown in FIGURE 2 a TF pulse may initiate a sub-cycle ofoperation, and will be followed by a TF thence the T P TF TR, and TF inthat sequence. Immediately after a final TF pulse an initial pulse TF ofthe next succeeding sub-cycle will appear. As shown in FIGURE 1 thetimed pulses are impressed upon the logic and ladder circuits and Thefinal pulse TF from the ring counter circuit 47 is passed via a lead toadvance the other ring counter 34 and it may be appreciated that a cycleof operation will commence when the ring counter 34 is set to render thetransistor 23 non-conduclive thereby impressing the reference potentialfrom the input terminal upon the amplifier input 27. In the next 6operations of the ring counter 4'7, constituting a first sub-cycle,pulses are passed over the various leads 4% to the ladder circuits whilethe ring counter 34- causes the reference potential from the terminal336 to be applied to the amplifier. At the conclusion of the sub-cycle aTF pulse will advance the ring counter 24 cutting off the transistor 29and thereby causing the analog input from the terminal ll to beimpressed upon the amplifier While this input continues to be impressedupon the amplifier, the ring counter'd? proceeds through anothersub-cycle of operation. Obviously, each time the ring counter 47 hascompleted a full sub-cycle, then the ring counter 34 will be againstepped or advanced to the next position for a similar sub-cycle ofoperation with the next analog input signal. The ring counter 34 rendersnon-conductive a selected one of the transistors through 32., and therefore, the ring counter 34, together with the transistors 28422constitute a switching means for selecting and impressing a single oneof the analog inputs upon the amplifier 115.

As indicated above, the ring counter 34 commences its cycle by applyingan appropriate voltage over a lead Elli to the base electrode of thetransistor This voltage is also conducted by the lead fit? to the logicand ladder circuits 36 to condition certain AND gates to pass the timedpulses from the counter 47. After the ring counter 34 has advanced pastits initial state, the lead it will become essentially ground potential,whereupon an inverter circuit 51 will generate and pass an appropriatevoltage over a lead 52 to condition other AND gates of the logiccircuits 39. Thus, it may be seen that the conditionin of the AND gatesof the logic circuits 36 or 39 is determined by the conduction state ofthe ring counter 34 such that during the initial sub-cycle the gates ofthe logic circuit 36 are conditioned to receive timing pulses, andduring the subsequent sub-cycles the gates of the logic circuit are soconditioned.

An understanding of the logic and ladder circuit 36 may be gained byreference to FIGURE 3. When the appropriate conditioning voltage isreceived on the terminal St), the timed pulses Tl through TF may passthrough the AND gates- 54 through 59. These AND gates may be of anyconventional type, the Richards book supra, discloses suitable diode ANDcircuits together with @R" circuits in Figure 21 on page 38.

As was indicated in connection with FIGURE 2 the first timing pulse of asub'cycle is TP which would pass through the conditioned AND circuit 54and through the OR circuits 6 3 through 63, and will reset the flip-flopcircuits through 67. These flip-flop circuits may likewise be of anyconventional design as for example the two triode circuits of Figure 33,page 71 or the transistorizcd circuits of pages 160 and 161 of theRichards book supra. When the flip-flop circuits are reset by pulsesapplied to the R terminals (lower left corner as shown in FEGURE 3), theflip flop assumes a first conduction state and may be considered as off.Thus, it becomes apparent that the TF pulse functions to reset or turnor all of the flipflcps of the logic circuit.

When the Ti, pulse appears and passes through the conditioned AND gate55, the flip-flop $64 is set or turned on thereby. As will be describedsubsequently when the flip-flop is on the voltage at terminal 1 is highto represent the highest order binary digit and the ladder circuit willgenerate a voltage corresponding to the highest order of digits. Thisvoltage will appear at the output terminal 6% and will be passed to thesumming point 27 of the amplifier 155 through the coupling resistor 37(see FlGURE l). The combined voltages from the reference potential point26 and from the highest order of digits from the ladder 3d are passed bythe amplifier l5 and the voltage level of the amplifier output terminal35 indicates whether the highest order of voltages was too small or toogreat as compared with the reference potential if the voltage is toogreat, an AND gate 7' will be conditioned to receive and pass the nexttiming pulse TF In such case the TF pulse will pass through the OP.circuit to reset the flip-flop 64 and thereby eliminate or reject thehighest order voltage. 011 the other hand, if the highest order voltagewere insufiicient to properly balance the voltage from the terminal .36,then the AND gate 7d would not be conditionedto "ass the TF pulse; andas a result the flip-11013 64 would remain on and the highest ordervoltage would not be rejected.

The TP pulse therefore functions to selectively reset the flip-flop 64and thereby to se ectively reject the highest order voltage. inaddition, the TF pulse is passed through the AND gate :56 to set or turnon the second flip-flop as. The flip-flop 65 controls the second ordervoltage, and therefore, when the first order of voltage is selectivelyrejected or accepted t e second order of voltage will appear eitheralone or combined with the highest order voltage. As in the first caseabove, the voltage at the output terminal 35 of the amplifier 15 willeither condition or fail to condition the AND circuit, '71, and the nextsuccessive timing pulse, TF will, therefore, selectively either passthrough the AND gate 71 to reset the flip-flop 65 and reject the secondorder voltage or will fail to pass that AND gate thereby accepting thevoltage. By similar logic we may consider the setting or turning on ofthe subsequent flip-flops 66 and 67 and the selective acceptance orrejection of each digital voltage in a descending order of digits.

At the conclusion of each sub-cycle, the state of the flip-flops 64through 67 cause the ladder circuit 75 to generate the selected combinedvoltages which will most closely balance the input voltage from theterminal 26. These voltages are developed by a ladder network comprisingresistors 76 through 82. The resistors 76 through 79 are each coupled topositive or negative voltage supplies 83 and 84 by pairs of transistors85 through 92. Each pair of transistors functions as a single pole,double throw switch such that the resistor connected to the mid pointtherebe-tween may be considered as connected either to the negative 20volts of terminal 83 or the positive 20 volts of terminal 84. The baseelectrodes of the transisters of each pair are coupled to thecorresponding flipflop circuits 64 through 67 by resistors 94 through101. Considering the first pair of transistors 85 and 86, we mayappreciate that one of the base electrodes is coupled to a high positivevoltage while the other is coupled essentially to a zero voltagedepending on whether the flipflop is on or off. Thus, one of thetransistors of each pair will be biased into conduction while the othertransistor of the pair will be biased into non-conduction. Thetransistor which conducts will present a very low impedance amounting toa closed switch while the other transistor, which is non-conductive,will present a very high impedance amounting to an open circuit.Therefore, the point 103 connected between the two emitter electrodes oftransistors 85 and 86 will be substantially at either a negative 20volts or a positive 20 volts depending upon the conduction state of theflip-flop 64.

In a particular circuit constructed, the voltages of terminals 83 and 84Were established as plus and minus 20 volts because of considerationswhich are not a part of this invention. It may be appreciated thatdifferent voltage standards can be established and that the transistorpairs and the ladder network will function equally well therewith.

The ladder network 75 comprises the serially connected resistors 80, 81,and 82 which are all equal to each other in resistive value. Theresistors 76, 77, 78 and 79 are equal in value to each other but areeach equal to twice the resistive values of each of the seriallyconnected resistors 80, 81 and 82. Obviously, the greatest contributionto the current output at the terminal 69 would be made when theflip-flop 64 is on such that the transistors 86 conducts and thepotential at point 103 becomes substantially 20 volts. Because of thechoice of the resistive values, the switching of the next seriesconnection point 104 to the positive 20 volts which contributes onlyhalf of the current output which was contributed through the resistor76. Contributions through the resistors 78 and 79 are likewise relatedaccording to the binary numbering system, and therefore the totalcurrent output from the ladder circuit corresponds to a binary numberwhich may be derived from those flip-flops which remain on aftercompletion of a sub-cycle.

The logic and ladder circuits 39 are substantially the same as thecircuits 36 but with slight differences which .will be pointed out. Thedigital output signals from the circuits 39 are developed by theflip-flops 64 through 67 and will appear on the digital output leads 31through 34 at the end of each sub-cycle of operation and will correspondto the voltage selectively developed by the ladder network 75 and withthe particular analog input signal selected by the ring counter 34.FIGURE 3 shows the digital outputs as being derived from the l outputsof the flip-flops, but this output may also be taken from the 0 outputs,or from the combined outputs of each flipfiop if this is compatable withthe further digital circuits (not shown) which may be coupled to receivethe output signals.

circuit 36 has developed a correction voltage corresponding to thecircuit error which may have been introduced by the transistor input 28through 32 and by the amplifier 15. As described heretofore this digitalcorrection is stored in the flip-flops 64 through 67 on the circuit 36and causes the correction voltage to be impressed from the summing pointof the amplifier 15. These flip-flops 64 through 67 constitute a digitalstorage means for storing the correction voltage which will continue tobe impressed upon the amplifier throughout the remainder of the cyclewhile the analog voltages are impressed sequentially from the amplifier.Although the ladder circycle.

cuit 36 continues to impress its correction voltage throughout the wholecycle of operation, the logic and ladder circuits 39 is re-set to zeroafter a read-out of the digital information at the conclusion of eachsub-cycle. At the completion of the final sub-cycle the flip-flops 64through 67 of the circuits 39 are re-set prior to the commencement ofthe next full cycle of operation, and particularly the circuits 39 arere-set prior to the initial sub-cycle when the correction voltage isbeing developed by the circuits 36. Therefore, the voltage developed bythe circuits 36 continues to be impressed on the amplifier 15 while thecircuits 39 are operative, but the circuits 39 are re-set and develop novoltage while the circuits 36 are operative during the first sub-cycle.

This slight difference in the operation of the logic and ladder circuits39 may be accomplished by changing the timing pulse connections tocircuits 39. The final pulse TF of each sub-cycle (excepting the firstsub-cycle) may be applied to the AND gate 54 of the circuits 39 tore-set the flip-flops 64 through 67. Then, the first timing pulse TP ofeach sub-cycle will be applied to the AND gate 55 to set or turn on theflip-flop 64. During the remainder of each of the sub-cycles, the logiccircuits 39 function the same as the circuits 36 described heretofore,except that each timing pulses TP through TF is shifted to the nextsuccessive AND gate 55 through 59. Thus, the sub-cycle is essentiallycompleted by the timing pulse TF at which time a digital read-out may beaccomplished. The final timing pulse TF then resets the circuit 39 tozero in preparation for the next sub-cycle of operation.

For the purpose of simplicity of description and understanding of thisinvention the number of analog inputs 11, 12, 13 and 14 have beenlimited to four. However, in the actual practice of this inventionfurther analog inputs may be incorporated into this system by the mereaddition of two serially connected resistors and a shunting transistorfor each additional input, and by enlarging the ring counter 34 toincrease the number pulses in each When the transistors '29 through 32conduct, the voltage at the serial connection point between theresistors will drop to substantially ground voltage. Each transistorwill contribute a slight error voltage to the input circuit, andalthough a large number of inputs will produce a substantial error, thisinvention provides a means for correcting this input error as well aserror due to drift of the amplifier. By one of this invention the inputand amplifier drift errors are essentially eliminated and no limit isforeseeable to the number of analog inputs that may be applied to such atime sharing, multiplexed conversion circuit. Indeed, this apparatus hasbeen built and successfully tested using a total of one hundredanaeconomy in manufacture is eifected.

To afford a further ease in description and understanding of thisinvention, the number of flip-flops 64 through 67 has been limited tofour, but in actual practice it is desirable to increase this number toobtain a greater accuracy of the digital output signal. The circuit ofFIG- URE 3 having four flip-flops may produce an error ratio of 1 to 16,and this accuracy could not be tolerated in most computer applications.'The apparatus built by this inventor contained 10 flip-flops in each ofthe digital logic circuits-36 and 39, and therefore, the output errorratio was theratio of 1 to 1,024 or expressed as percent the apparatusshould produce an error of less than 0.1%. Obviously, this apparatus maybe designed for any desired accuracy (assuming a corresponding accuracyin the input resistors and amplifier components) by merely providing thecorrect number of'flip-flop circuits and the attending circuitry asindicated in FIGURE 3 together with a corresponding enlargement of thering counter -57 to yield an increase in-the number of clock pulses TPTP TP TP The digital arrangement of circuit 36 for developing acorrection voltage and for storing and retaining that correction voltagethroughout a cycle of operation provide a greater degree of accuracythan an analog voltage storage arrangement. This digital voltage storagedoes not depend for accuracy upon the charging of a capacitor, or thelike; and therefore, the voltage may be stored for an indefinite periodof time without deterioration from leakage currents or such.

While the ladder circuit 75 is considered to be a conventional binaryarrangement, it may be appreciated that other forms of digital voltagegeneration in accordance with a numbering system could be used in thisinvention. Thus, for example, if a ladder circuit were devised utilizinga decimal logic rather than a binary logic, then this invention could bepracticed essentially as shown and described heretofore but couldproduce a decimal output.

Changes may be made in the form, construction and arrangement of theparts without departing from the spirit of the invention or sacrificingany of its advantages, and the right is hereby reserved to make all suchchanges as fall fairly within the scope of the following claims.

What is claimed is:

1. Apparatus for converting analog signals representative of numericalquantities into digital signals corresponding to the numericalquantities, said apparatus comprising an input means for receiving andselectively passing the analog signals, a first digital voltagegenerating means, and asecond digital voltage generating means, saidinput means being initially operable to pass a reference voltage, saidfirst digital voltage generating means being operable to develop anddigitally store a correction voltage when the reference voltage ispassed by the input means, said second digital voltage generating meansbeing operable to develop a voltage when a selected analog signal ispassed by the input means, said second digital voltage generating meansbeing further operable to develop a digital output signal correspondingto the voltage developed thereby.

2. Apparatus for converting analog signals representative of numericalquantities into digital signals correspond ing to the numericalquantities, said apparatus comprising an input switch means forreceiving and selectively passing the analog signals, a first digitalladder circuit for generating a voltage, said input switching meansbeing initially operable to pass a reference voltage and said digitalladder circuit being operable to develop a correction voltage when thereference voltage is passed by the input switching means, a seconddigital ladder circuit operable to generate a voltage corresponding tothe selected analog signal and further operable to generate a digitaloutput signal corresponding to. the voltage thereby generated.

3. Apparatus for converting analog signals representative of numericalquantities into digital signals corresponding to the numericalquantities, said apparatus comprising an input switching means forreceiving and selectively passing the analog signals, a circuit meanscoupled to the input switching means, a first digital voltage generatingmeans for generating voltage in accordance with a digital numberingsystem, said switching means being initially operable to impress areference potential upon the circuit means, said first digital voltagegenerating means being responsively coupled to the circuit means andbeing operable to develop a correction voltage corresponding to thereference potential, meansfor coupling the correction voltage to thecircuit means, and a second digital voltage generating means forgenerating successive voltages in accordance with the digital numberingsystem, said input switching means being operable to impress the analogsignals upon the circuit means, and said second voltage generating meansbeing responsive to the circuit means and being operable to establish adigital output and a voltage corresponding to the analog signal.

4. Apparatus for converting analog signals representative of numericalquantities into digital signals corresponding to the numericalquantities, said apparatuscomprising an input switching means forreceiving and selectively passing the analog signals, an amplifyingcircuit coupled to the input switching means, a first ladder circuit forgenerating successive voltages corresponding to a digital. numberingsystem, said input switching means being initially operable to pass areference voltage to the amplifying circuit and said first laddercircuit being operable to generate and selectively reject the digitalvoltages to develop a correction voltage corresponding to an errorresulting from the input switching means and the amplifying circuit,said input switching means being subsequently operable to selectivelypass the analog signals to the amplifying circuit, a second laddercircuit operable to generate voltages in accordance with the digitalnumbering system, said second ladder circuit being further operable toselectively reject the Voltages generated to develop the voltagecorresponding to the selected analog signal and to generate a digitaloutput signal in accordance with the voltage thereby developed.

5. Apparatus for converting analog signals representative of numericalquantities into digital signals corresponding to the numericalquantities, said apparatus comprising an input switching means forreceiving and selectively passing the analog signals, an amplifyincircuit having an input summing point coupled to the input switchingmeans, said input switching means being initially operable to pass areference voltage to the summing point of the amplifying circuit andbeing subsequently operable to sequentially pass the analog signalsthereto, a first ladder circuit coupled to the summing point of theamplifying circuit, said first ladder circuit being operable to generatesuccessive voltages having a binary relationship with each other, ameans associated with the first ladder circuit and responsive to signalsfrom the amplifier for selectively rejecting the binary voltages wherebythe first ladder circuit will develop a correction voltage corre--sponding to a degree of error resulting from the input switching meansand from the amplifier, and a second ladder circuit for generaitingsuccessive voltages having a binary relationship with each other, saidsecond ladder circuit being coupled to the summing point of theamplifier whereby the successive binary voltages are summed with theanalog signals from the input switching means and with the correctionvoltage from the first ladder circuit, said second ladder circuit havingmeans associated therewith for selectively rejecting voltages whichexceed the analog signal and for developing a binary output signal.

6. Apparatus for converting analog signals representative of numericalquantities into digital signals corresponding to the quantities, saidapparatus comprisingan input switching means for receiving andselectively passing the analog signals, said input switching meansinclud ing a plurality of impedance devices for receiving the analogsignals, a controllable conduction device coupled between the impedancedevice and a sourceof reference potential for providing a shunt path forthe analog signals, an amplifier having an input circuit with a summingpoint, each of the impedance devices and the controllable conductiondevice of the input switching means being coupled to the summing pointof the amplifier whereby the analog signals may be selectively coupledto or by-passed from the amplifier, a digital means for developing avoltage coupled to the summing point of the amplifier, said inputswitching means having one impedance device initially operable to pass areference voltage to the summing point of the amplifier, and said firstdigital voltage generating means being operable to correct any errorintroduced by the input switching means and the amplifier.

7. Apparatus for converting analog signals representative of numericalquantities into digital signals corresponding to the quantities, saidapparatus comprising an input switching means, an amplifier having aninput summing point, and a digital ladder circuit coupled to the summingpoint of the amplifier, said input switching means including a pluralityof impedance paths for passing the analog signals to the summing pointof the amplifier, and a plurality of controllable conduction devices forselectively by-passing the analog signals away from the summing point ofthe amplifier, one of the impedance paths of the input switching meansbeing coupled to impress a reference potential upon the summing point ofthe amplifier, and one of the controllable conductive devices beingoperable to permit the reference voltage to pass to the amplifier at thebeginning of a cycle of operation, said digital ladder circuit beingoperable to develop a correction voltage and impress said correctionvoltage upon the summing point of the amplifier in response to thereference potential thereupon.

8. Apparatus for converting analog signals representative of numericalquantities into digital signals corresponding to the quantities, saidapparatus comprising an input switching means, an amplifier having aninput summing point, and a first digital ladder circuit and a seconddigital ladder circuit both coupled to the summing point of theamplifier, said input switching means including a plurality of impedancecoupling devices each operable to pass a corresponding one of the analogsignals to the summing point of the amplifier, a controllable conductiondevice coupled to each of the impedance coupling devices for selectivelydisabling the impedance coupling devices and blocking the analog signalfrom the summing point of the amplifier, a stepping circuit coupled tothe controllable conduction devices and operable to render the devicesnon-conductive in a pre-determined order, a first order impedancecoupling device being coupled to pass a reference potential to thesumming point of the amplifier, the stepping circuit being operable toinitially select and impress the reference potential upon the amplifierand to subsequently select signals for application to the amplifier, thefirst digital ladder circuit being operable to provide a correctionvoltage to the amplifier, and the second digital ladder circuit beingoperable to provide digital output signals in accordance with theselected analog signal.

9. Apparatus for converting analog signals representative of numericalquantities into digital signals corresponding to the quantities, saidapparatus comprising an input switching means, an amplifier having aninput summing point, and a first digital ladder circuit and a seconddigital ladder circuit both coupled to the summing point of theamplifier, said input switching means including a plurality of impedancecoupling devices each operable to pass a corresponding one of the analogsignals to the summing point of the amplifier, a controllable conductiondevice coupled to each of the impedance coupling devices for selectivelydisabling the impedance coupling devices and blocking the analog signalfrom the summing point of the amplifier, a digital counter circuitcoupled to each of the controllable conduction devices and operable torender non-conductive the controllable conduction devices in asequential order, a first of the impedance cou ling devices beingcoupled to a point of reference potential whereby the referencepotential is impressed upon the summing point of the amplifier toinitiate a cycle of operation, the first digital ladder circuit beingresponsive to signals from the amplifier and being operable to develop acorrection voltage at the summing point to correct any error resultingfrom the input switching means and the amplifier, the second digitalladder circuit being responsive to signals from the amplifier and beingoperable to impress a voltage in accordance with a digital numberingsystem upon the summing point and being further operable to develop adigital output signal in accordance with the voltage impressed upon thesumming point of the amplifier.

10. Apparatus for converting analog signals representative of numericalquantities into digital signals corresponding to the quantities, saidapparatus comprising an input switching means, an amplifier having aninput sum ming point, and a first digital ladder circuit and a seconddigital ladder circuit both coupled to the summing point of theamplifier, said input switching means including a plurality of resistivenetworks each operable to pass a corresponding one of the analog signalsto the summing point of the amplifier, a transistor coupled to each ofthe resistive networks whereby the analog signals may be bypassed toground through conduction of the transistor, a ring counter circuitcontrollably coupled to the transistors and operable to drive all but aselected one of the transistors into conduction, a first of theresistive networks being coupled to a point of reference potentialwhereby the reference potential is impressed upon the summing point ofthe amplifier to initiate a cycle of operation, the first digital laddercircuit being operable during the time when the reference potential isapplied to the amplifier for developing a voltage to correct any errorswhich may be introduced into the circuit by the input switching meansand by the amplifier and being further operable during the remainder ofthe cycle to continue to impress the correction voltage upon theamplifier, said second digital ladder circuit being responsive tosignals from the amplifier and being operable to impress a voltage inaccordance with a digital numbering system upon the summing point andbeing further operable to develop a digital output signal in accordancewith the voltage thereby impressed upon the summing point.

11. The apparatus according to claim 10 and further comprising a meanscoupling the ring counter circuit to the first and second digital laddercircuits, said coupling means being operable to render the first laddercircuit operative during the time when the first of the resistivenetworks impresses the reference potential upon the summing point of theamplifier, said coupling means being further operable to render thesecond digital ladder circuit operative during the remainder of thecycle of operation when the reference potential is not impressed uponthe summing point of the amplifier.

References Cited in the file of this patent UNITED STATES PATENTS2,945,220 Lesti et al July 12, 1960 2,947,971 Glauberman Aug. 2, 19602,965,891 Martin Dec. 20, 1960 3,027,079 Fletcher et a1 Mar. 27, 19623,070,786 MacIntyre Dec. 25, 1962 OTHER REFERENCES Slaughter: TimeShared Amplifier Stabilizes Computers, Electronics, April 1954, (pp.188-190).

9. APPARATUS FOR CONVERTING ANALONG SIGNALS REPRESENTATIVE OF NUMERICALQUANTITIES INTO DIGITAL SIGNALS CORRESPONDING TO THE QUANTITIES, SAIDAPPARATUS COMPRISING AN INPUT SWITCHING MEANS, AN AMPLIFIER HAVING ANINPUT SUMMING POINT, AND A FIRST DIGITAL LADDER CIRCUIT AND A SECONDDIGITAL LADDER CIRCUIT BOTH COUPLED TO THE SUMMING POINT OF THEAMPLIFIER, SAID INPUT SWITCHING MEANS INCLUDING A PLURALITY OF IMPEDANCECOUPLING DEVICES EACH OPERABLE TO PASS A CORRESPONDING ONE OF THE ANALOGSIGNALS TO THE SUMMING POINT OF THE AMPLIFIER, A CONTROLLABLE CONDUCTIONDEVICE COUPLED TO EACH OF THE IMPEDANCE COUPLING DEVICES FOR SELECTIVELYDISABLING THE IMPEDANCE COUPLING DEVICES AND BLOCKING THE ANALOG SIGNALFROM THE SUMMING POINT OF THE AMPLIFIER, A DIGITAL COUNTER CIRCUITCOUPLED TO EACH OF THE CONTROLLABLE CONDUCTION DEVICES AND OPERABLE TORENDER NON-CONDUCTIVE THE CONTROLLABLE CONDUCTION DEVICES IN ASEQUENTIAL ORDER, A FIRST OF THE IMPEDANCE COUPLING DEVICES BEINGCOUPLED TO A POINT OF REFERENCE POTENTIAL WHEREBY THE REFERENCEPOTENTIAL IS IMPRESSED UPON THE SUMMING POINT OF THE AMPLIFIER TOINITIATE A CYCLE OF OPERA-